Generally, computers may use various types of memory devices to store data. For example, in the past, some computers were manufactured by mounting memory devices directly on a main board. However, as recent trends have seen a reduction in the size of computers coupled with an increase in structural complexity, higher-speed, larger-capacity memory devices may be required. As such, it may be difficult to mount larger numbers of memory devices on the existing main board.
Accordingly, memory modules on which a plurality of memory devices can be installed have been proposed. FIG. 1A illustrates the structure of a conventional memory module 100. The conventional memory module 100 includes a body 110 on which a plurality of memory chips CP are mounted, and a plurality of contacts 120 for signal transmission. The conventional memory module 100 may be a single in-line memory module (SIMM) or a dual in-line memory module (DIMM), according to the arrangement of the contacts 120.
In general, a SIMM may include 72 pins and may support transmission of 32-bit data, while a DIMM (which may be a two-folded SIMM) may include 168 pins and may support transmission of 64-bit data.
FIG. 1B illustrates the structure of a conventional DIMM. Referring now to FIG. 1B, a front portion 120A and a back portion 120B of each contact 120 of the DIMM are electrically separated from each other. Thus, signals input to the front portion 120A of each contact 120 can be input to a memory chip CP mounted on a body 110, and signals passing through the memory chips CP can be output via the back portion 120B of each contact 120.
FIGS. 2A and 2B illustrate examples of the flow of input signals to memory chips CP1 through CP4 that may be mounted on a memory module. Referring to FIG. 2A, a signal S received via a contact of the memory module branches twice for distribution to the memory chips CP1 through CP4. In contrast, as shown in FIG. 2B, a signal S received via a contact of a memory module branches only once for distribution to memory chips CP1 through CP4.
Since the signal S may branch one or more times during transmission from the contact to the inputs of the memory chips CP1 through CP4, the signal S may be received by the chips CP1 through CP4 at different times, depending on the respective locations of the memory chips CP1 through CP4 on the memory module.
FIG. 3A illustrates another example of the flow of a signal S to be input to first through fourth memory chips CP1 through CP4 that may be mounted on a memory module. Referring now to FIG. 3A, the signal S received via a contact (not shown) of the memory module is input to the first memory chip CP1, passes through the first memory chip CP1, and is input to the second memory chip CP2. Likewise, the signal S passes through the second memory chip CP2, and is sequentially input to the third and fourth memory chips CP3 and CP4. As shown in FIG. 3A, the manner in which the signal S is input is referred to as a “daisy chain” transmission scheme. The signal S may include serial data.
FIG. 3B illustrates the structure of a memory chip CP, which may correspond to one of the memory chips CP1 to CP4 as shown in FIG. 3A. For the daisy chain signal transmission scheme illustrated in FIG. 3A, the memory chip CP may be fabricated such that pins used for input and output of a write signal WS from the memory chip CP during a write operation may be different from the pins used for input and output of a read signal RS from the memory chip CP during a read operation. In other words, as shown in FIG. 3B, the write signal WS to be input to the memory chip CP during the write operation is input to a write signal receiving unit WRX of the memory chip CP, and is output via a write signal transmitting unit WTX. Similarly, the read signal RS to be input to the memory chip CP during the read operation is input to a read signal receiving unit RRX of the memory chip CP, and is output via the read signal transmitting unit RTX.
FIG. 4 illustrates a memory system 400 including first through fourth memory modules MM1 through MM4 on which memory chips according to FIG. 3B are mounted. The memory system 400 includes the first through fourth memory modules MM1 through MM4, and a host 410. The host 410 may be a memory controller. During a write operation, a write signal WS output from the host 410 is input to a memory chip CP11 of the first memory module MM1. Then (as similarly illustrated in FIG. 3A), the write signal WS input to the memory chip CP11 is transmitted to memory chip CP12 adjacent to the memory chip CP11. Likewise, the write signal WS is serially transmitted through memory chips CP13, CP14, and C15, and is then output from the last memory chip CP15.
The write signal WS output from memory chip CP15 is input to a last memory chip CP25 of the second memory module MM2, is serially transmitted through memory chips CP24, CP23, CP22, and CP21, and is input to the third memory module MM3 via memory chip CP21. The write signal WS is similarly input to the fourth memory module MM4, and is input to a next memory module (not shown) via a first memory chip CP41 of the fourth memory module MM4.
In contrast, during a read operation, a read signal RS is first input to the first memory chip CP41 of the fourth memory module MM4. Then (as similarly illustrated in FIG. 3A), the read signal RS is output from the memory chip CP41, serially transmitted to adjacent memory chips CP42, CP43, CP44, CP45, and finally output from the last memory chip CP45 of the fourth memory module MM4.
The output read signal RS is input to a last memory chip CP35 of the third memory module MM3, serially transmitted through memory chips CP34, CP33, CP32, and CP31, and input to the second memory module MM2 via the first memory chip CP31. Similarly, the read signal RS is serially transmitted through memory modules MM2 and MM1, and finally input to the host 410 via the first memory chip CP11 of the first memory module MM1.
Accordingly, FIG. 4 illustrates the layout of a memory module including memory chips in which the pins used for input and/or output of a write signal WS during a write operation are different from the pins used for input and/or output of a read signal RS during a read operation. As shown in FIG. 4, the configuration of the first memory module MM1 is the same as that of the third memory module MM3, and the configuration of the second memory module MM2 is the same as that of the fourth memory module MM4. However, because the pins used for input and/or output in the first and third memory modules MM1 and MM3 are different from those of the second and fourth memory modules MM2 and MM4, the configurations of the first and third memory modules MM1 and MM3 are different from those of the second and fourth memory modules MM2 and MM4.
As such, when a memory system is constructed using memory modules with memory chips such as those illustrated in FIG. 3B, two or more types of memory modules having different configurations and/or structures may be required.